1. Technical Field
This disclosure relates to delay circuitry and more particularly, to a delay element using a delay locked loop to generate digital pointers for matching delays in other circuits.
2. Description of the Related Art
Delay locked loops (DLL) are employed to compare a periodic signal input signal with an output signal. In this way a phase difference between the signals can be set to about zero. Referring to FIG. 1, a conventional DLL 10 is shown. An input signal CKin is input to a delay line 12 and a phase comparator 14. An output signal CKout is compared with input signal CKin by employing phase comparator 14. Phase comparator 14 sets or adjusts delay line 12 to provide a zero phase difference between the input and output signals. Delay line 12 stabilizes when the delay between input CKin and output CKout signals reaches a clock period T or a multiple thereof (kT, where k is a natural number). DLL 10 may be employed to synchronize an input clock to an output clock on a given integrated circuit, for example.
Referring to FIG. 2, an application of a DLL is shown. DLL 20 includes delays introduced by a receiver 22 and by a driver 24. These delays are compensated for by a delay element 26. Delay element 26 provides a delay compensation of .tau. in a feedback loop where .tau.=R+D. R is the delay introduced by receiver 22, and D is the delay introduced by driver 24. Input and output clocks, CKin and CKout, respectively, are synchronized when their phase difference becomes 2 k.pi., that is, when the delay between input and output signals is equal to a multiple of the clock period, i.e., kT. Then, phase comparator 14 detects no phase difference between its two inputs 25 and 27. Input 25 has a delay of R compared to input clock (CKin). Input 27 has a delay of kT+R compared to input clock (CKin), where T is the clock period. In the case shown and described with respect to FIG. 2, the delay line control signal (pointer) 30 is adjusted until inputs 25 and 27 are in sync.
Referring now to FIG. 3, a more specific use for a DLL is illustrated. A circuit 40 is employed to synchronize an output data stream DQout. Output data DQ is latched in a D Flip Flop (DFF) by a DLLCLK signal. The delay is the sum of receiver delay R, driver delay D and the delay introduced by Flip Flop DFF.
Referring to FIG. 4, circuit 40 of FIG. 3 can be adapted to provide double data rate output using the DLL to multiply the clock frequency by 2. A DLL system 50 produces a clock signal with a double frequency of the input clock such that the output data (DQout) is in phase with the input clock (CKin) as described above. To perform this, two clock signals are derived from input clock signal CKin. The first derived signal has a delay of kT-D where D is the sum of delays of an OR gate 52, flip-flop DFF and output driver 24. The second derived clock signal has a delay of (3 kT/2)-D. Both the first and second derived clock signals are input to OR gate 52. For the second derived signal, a second delay line 54 is employed which is controlled by a pointer P/2 (having half the value of a pointer P controlling delay line 12 from phase comparator 14. A delay element 57 is introduced to provide delay to input 53. In this case, the DLL is digital, which means that pointer P may be divided by two by dropping the least significant bit (LSB). This ensures that the delay caused by delay line 54 is half the delay introduced by delay line 12.
The delay introduced by delay line 12 is kT-D-R. The delay introduced by delay line 54 is (kT-D-R)/2. So the delay of the signal incoming at an input 53 of OR gate 52 is (kT-D)+(kT-D-R)/2+(R+D)/2=(3kT/2)-D. This ensures the generation of the second clock on input 53 with a phase shift of 180 degrees to the first clock on input 55.
A problem related to DLL system 50 is that it is difficult to track delay elements for all the process and temperature variations of the receiver and the driver circuits. It is even more difficult to generate another circuit tracking, in the same manner, half of this delay to provide the double data rate.
Therefore, a need exists for a delay element including a delay locked loop which provides better tracking of delays introduced in the circuit. A further need exists for a delay locked loop circuit to provide tracking a half delay clock signal.